Wire bonding processes have been simulated in the past, but most simulations have been theoretical studies with little practical applications. For example, a wire bonding operation may be simulated using finite element analysis (FEA) software (e.g., ANSYS®, ALGOR®). Results from an FEA may be useful in performing failure analysis of a wire bond and/or failure analysis of a chip receiving the wire bond, for example.
For some FEA software, the inputs are capillary design (e.g., geometry, material properties), capillary displacement, and wire properties (e.g., wire diameter, initial free air ball size, yield strength), for example. However, such inputs are not very practical because the actual inputs, settings, and/or adjustments found on a typical wire bonding machine are often much different. Some example parameters set or adjusted on a typical wire bonding machine by an operator include ultrasonic energy, ultrasonic current, scrub time, and capillary force, for example.
Because the wire bonding machine adjustment parameters generally do not match up with the input parameters needed by most FEA software, failure analysis on a chip being wire bonded is often performed by trial and testing of actual chips. This can be rather costly and time consuming. Often it would be more desirable to perform the failure analysis using FEA simulations. Also, incorporating wire bonding process information into the design rules for chip layout so that the chip may be designed according to such rules would be preferred in most cases, rather than performing trial and error testing. It would thus be desirable to provide a more practical application of a wire bonding simulation. Hence, a need exists for a way to estimate (through simulation) stresses exerted on a chip during a wire bonding process using the wire bonding machine adjustment parameters as inputs.